1. Field of the Invention
The present invention relates to a semiconductor element for electrical power control, such as for motor control, a power circuit, or illumination control, and more particularly to a power MOS transistor that is highly pressure-resistant and is for use with a high current.
2. Description of Related Art
Conventionally, as one example of the constitution of a power MOS transistor, a lateral power MOS structure is known, which appears in Document 1 (Document 1: Proceedings International Symposium on Power Semiconductor Devices and IC""s, Tokyo, pp.322-327: A 1200V BiCMOS TECHNOLOGY AND ITS APPLICATIONS), for example. In addition, ICs (intelligent power elements), in which a lateral power MOS transistor of this kind and a control circuit are mounted on a chip, are well known.
The structure of the lateral power MOS transistor of Document 1 will be described hereinbelow in a straightforward manner with reference to FIG. 6(A) and FIG. 6(B).
In FIG. 6(A) and FIG. 6(B), the reference numeral 100 represents a conventional lateral power MOS transistor. An N well layer 104, which constitutes a drain, is formed at a given depth, in a thickness direction, from the surface of a P-type semiconductor substrate 102. Within this N well layer 104, a drain N+ diffusion layer 106 is formed, and SiO2 films 108 and 108x are respectively formed on both sides of drain N+ diffusion layer 106. A source N+ diffusion layer 110 is provided in the surface of substrate 102 and a gate oxide film 112 is provided on substrate 102 and between source N+ diffusion layer 110 and N well layer 104. Within N well layer 104 which is beneath the SiO2 film 108x that is between gate oxide film 112 and drain N+ diffusion layer 106, a P+ layer 114 is formed. A gate electrode 116 is formed on gate oxide film 112. A drain electrode 118 is provided on drain N+ diffusion layer 106. A source electrode 120 is formed on source N+ diffusion layer 110. Drain electrode 118 and source electrode 120 are aluminum wiring. Consequently, this wiring 118 and 120 are isolated by a PSG film 122, which is provided above substrate 102. In addition, a passivating film 124 is formed so as to cover drain electrode 118 and source electrode 120, and PSG film 122.
In order to furnish this transistor 100 with high pressure-resistance characteristics, N well layer 104, which constitutes a drain, is formed at a given depth in the thickness direction of the substrate. As a consequence, it is possible to alleviate an electric field of a magnitude from several tens of volts to several hundreds of volts, or occasionally several thousands of volts, which is applied to drain 104.
SiO2 film 108x is provided at the upper face of N well layer 104 and so as to adjoin gate oxide film 112. This SiO2 film 108x serves to permit a high electric field to be released from drain 104 to gate electrode 116, and also makes it possible to prevent the destruction, by a high electric field, of the insulation constituted by gate oxide film 112.
Furthermore, P+ layer 114 is formed beneath the SiO2 film 108x that is between gate oxide film 112 and drain N+ diffusion layer 106. As a result, requirements are satisfied for the basic constitution of a junction-type FET 150 in which this P+ layer 114 and substrate 102 constitute a gate, drain N+ diffusion layer 106 is a drain, and source N+ diffusion layer 110 is a source. Also, a depletion layer is formed that extends from the gate region of this junction-type FET 150 to the channel region constituted by N well layer 104. This depletion layer fulfils the task of releasing the electric field from the drain. Consequently, operation by the lateral power MOS transistor within a high voltage range can be ensured.
Formation of junction-type FET 150 inside the lateral power MOS transistor discussed above whose structure is shown in FIGS. 6(A) and 6(B) is ultimately limited by the voltage drop of the drain current across this FET structure. As shown by the dotted line, the drain current enters FET 150 from drain electrode 118 and flows to the gate electrode and source electrode side of the MOS transistor via a channel portion (N well layer 104) of the junction-type FET. As a result, upon passing through the channel portion of the junction-type transistor, the drain current is subjected to channel resistance, whereby a decrease is generated, over a given unit period, in the drain current passing through the channel portion.
In attempting to achieve a large current in a power MOS transistor of this kind, normally gate length L may be made short and gate width W broad. However, in order for a high voltage to be employed, to prevent the channel being shortened by a high voltage, it is necessary to ensure a certain value for gate length L. Consequently, in order to permit a large current to flow in this power MOS transistor, a method is adopted of making gate width W broad.
Therefore, as a result of making gate width W broad, the surface area of the power MOS transistor increases. However, In an IC that comprises a lateral power MOS transistor of this kind, the power MOS transistor occupies 50-80% of the surface area of the chip. Consequently, the act of making gate width W broad involves an increase in the surface area of the chip. The increase in the chip surface area adversely affects the yield of the elements, the miniaturization of components, and the multi-functionality that is determined by the degree of integration and the on-chip mounting.
It is therefore an object of the present invention to provide a power MOS transistor that is capable of permitting a large current to flow without making the gate width broad.
It is a further object of the present invention to provide a power MOS transistor that has a structure allowing a good yield to be obtained for a highly integrated, multifunctional, miniature IC.
For this reason, the power MOS transistor of the present invention comprises a first-conductivity-type substrate; a second-conductivity-type well region; a second-conductivity-type first electrode region; a first-conductivity-type region; and a second-conductivity-type second electrode region.
The first electrode region and first-conductivity-type region are respectively provided so as to be spaced apart from one another within the well region. Further, the second electrode region is provided within the substrate. This first electrode region, first-conductivity-type region and second electrode region are respectively arranged in this order so as to be spaced apart from one another along a straight line (this straight line direction constitutes a first direction) when viewed in a planar direction. As a result of this arrangement, a main channel region is formed which extends from the first electrode region, along the underside of the first-conductivity-type region, and to the second electrode region.
Further, the first-conductivity-type region is constituted by a plurality of first-conductivity-type sub-regions, which are arranged so as to be spaced apart from one another in a second direction that is orthogonal to the above-mentioned first direction (from the first electrode region to the first-conductivity-type region and then to the second electrode region). Further, surface channel regions (also called channel sub-regions) are formed between these adjacent first-conductivity-type sub-regions.
A bulk junction-type FET (called a first junction-type FET) is constituted in the above-mentioned structure of the present invention, similarly to the prior art, by a gate, which comprises a substrate and a first-conductivity-type region; a drain, which comprises a first electrode region; and a source, which comprises a second electrode region. In addition, a surface junction-type FET (called a second junction-type FET) is constituted in the upper face of this structure by a gate, which comprises a first-conductivity-type region; channel sub-regions; a drain, which comprises a first electrode region; and a source, which comprises a second electrode region.
Therefore, the well region, which has portions that lie in the gaps between the first-conductivity-type sub-regions of this second junction-type FET structure, acts as a new drain current path in the power MOS transistor. Consequently, since it is possible to increase the drain current path to exceed that in a conventional structure, the drain current that is manageable can be increased. As a consequence, a large current flow in the transistor is permitted without a need to make the gate width broad.
Furthermore, since it is not necessary to make the gate width broad, there is also no increase in the size of the power MOS transistor. Therefore, since, in an IC that comprises a power MOS transistor of this kind, the surface area, within the chip, that is occupied by the power MOS transistor is ultimately small, a highly integrated, multifunctional, miniature IC can be provided. In addition, the yield is also good with an IC of this kind.